module nct_arr_8882( Z, X, Y);
input [7:0] Y;
input [7:0] X;
output [7:0] Z;
wire [1] zero =0 ;
wire [1] one =1 ;
wire [1] P0_7 = X[7] & Y[0];
wire [1] P0_6 = X[6] & Y[0];
wire [1] P0_5 = X[5] & Y[0];
wire [1] sum1_7 = X[7] & Y[1];
wire [1] P1_6 = X[6] & Y[1];
wire [1] P1_5 = X[5] & Y[1];
wire [1] P1_4 = X[4] & Y[1];
wire [1] sum2_7 = X[7] & Y[2];
wire [1] P2_6 = X[6] & Y[2];
wire [1] P2_5 = X[5] & Y[2];
wire [1] P2_4 = X[4] & Y[2];
wire [1] P2_3 = X[3] & Y[2];
wire [1] sum3_7 = X[7] & Y[3];
wire [1] P3_6 = X[6] & Y[3];
wire [1] P3_5 = X[5] & Y[3];
wire [1] P3_4 = X[4] & Y[3];
wire [1] P3_3 = X[3] & Y[3];
wire [1] P3_2 = X[2] & Y[3];
wire [1] sum4_7 = X[7] & Y[4];
wire [1] P4_6 = X[6] & Y[4];
wire [1] P4_5 = X[5] & Y[4];
wire [1] P4_4 = X[4] & Y[4];
wire [1] P4_3 = X[3] & Y[4];
wire [1] P4_2 = X[2] & Y[4];
wire [1] P4_1 = X[1] & Y[4];
wire [1] sum5_7 = X[7] & Y[5];
wire [1] P5_6 = X[6] & Y[5];
wire [1] P5_5 = X[5] & Y[5];
wire [1] P5_4 = X[4] & Y[5];
wire [1] P5_3 = X[3] & Y[5];
wire [1] P5_2 = X[2] & Y[5];
wire [1] P5_1 = X[1] & Y[5];
wire [1] P5_0 = X[0] & Y[5];
wire [1] sum6_7 = X[7] & Y[6];
wire [1] P6_6 = X[6] & Y[6];
wire [1] P6_5 = X[5] & Y[6];
wire [1] P6_4 = X[4] & Y[6];
wire [1] P6_3 = X[3] & Y[6];
wire [1] P6_2 = X[2] & Y[6];
wire [1] P6_1 = X[1] & Y[6];
wire [1] P6_0 = X[0] & Y[6];
wire [1] sum7_7 = X[7] & Y[7];
wire [1] P7_6 = X[6] & Y[7];
wire [1] P7_5 = X[5] & Y[7];
wire [1] P7_4 = X[4] & Y[7];
wire [1] P7_3 = X[3] & Y[7];
wire [1] P7_2 = X[2] & Y[7];
wire [1] P7_1 = X[1] & Y[7];
wire [1] P7_0 = X[0] & Y[7];
wire [1] carry1_6;
wire [1] sum1_6;
ha1a(carry1_6,sum1_6,P1_6,P0_7);
//adding SHA
wire [1] carry1_5;
wire [1] sum1_5;
fa1a(carry1_5,sum1_5,one,P1_5,P0_6);
wire [1] carry2_6;
wire [1] sum2_6;
fa1a(carry2_6,sum2_6,P2_6,sum1_7,carry1_6);
wire [1] carry2_5;
wire [1] sum2_5;
fa1a(carry2_5,sum2_5,P2_5,sum1_6,carry1_5);
wire [1] carry2_4;
wire [1] sum2_4;
fa1a(carry2_4,sum2_4,P2_4,sum1_5,P1_4);
wire [1] carry3_6;
wire [1] sum3_6;
fa1a(carry3_6,sum3_6,P3_6,sum2_7,carry2_6);
wire [1] carry3_5;
wire [1] sum3_5;
fa1a(carry3_5,sum3_5,P3_5,sum2_6,carry2_5);
wire [1] carry3_4;
wire [1] sum3_4;
fa1a(carry3_4,sum3_4,P3_4,sum2_5,carry2_4);
wire [1] carry3_3;
wire [1] sum3_3;
fa1a(carry3_3,sum3_3,P3_3,sum2_4,P2_3);
wire [1] carry4_6;
wire [1] sum4_6;
fa1a(carry4_6,sum4_6,P4_6,sum3_7,carry3_6);
wire [1] carry4_5;
wire [1] sum4_5;
fa1a(carry4_5,sum4_5,P4_5,sum3_6,carry3_5);
wire [1] carry4_4;
wire [1] sum4_4;
fa1a(carry4_4,sum4_4,P4_4,sum3_5,carry3_4);
wire [1] carry4_3;
wire [1] sum4_3;
fa1a(carry4_3,sum4_3,P4_3,sum3_4,carry3_3);
wire [1] carry4_2;
wire [1] sum4_2;
fa1a(carry4_2,sum4_2,P4_2,sum3_3,P3_2);
wire [1] carry5_6;
wire [1] sum5_6;
fa1a(carry5_6,sum5_6,P5_6,sum4_7,carry4_6);
wire [1] carry5_5;
wire [1] sum5_5;
fa1a(carry5_5,sum5_5,P5_5,sum4_6,carry4_5);
wire [1] carry5_4;
wire [1] sum5_4;
fa1a(carry5_4,sum5_4,P5_4,sum4_5,carry4_4);
wire [1] carry5_3;
wire [1] sum5_3;
fa1a(carry5_3,sum5_3,P5_3,sum4_4,carry4_3);
wire [1] carry5_2;
wire [1] sum5_2;
fa1a(carry5_2,sum5_2,P5_2,sum4_3,carry4_2);
wire [1] carry5_1;
wire [1] sum5_1;
fa1a(carry5_1,sum5_1,P5_1,sum4_2,P4_1);
wire [1] carry6_6;
wire [1] sum6_6;
fa1a(carry6_6,sum6_6,P6_6,sum5_7,carry5_6);
wire [1] carry6_5;
wire [1] sum6_5;
fa1a(carry6_5,sum6_5,P6_5,sum5_6,carry5_5);
wire [1] carry6_4;
wire [1] sum6_4;
fa1a(carry6_4,sum6_4,P6_4,sum5_5,carry5_4);
wire [1] carry6_3;
wire [1] sum6_3;
fa1a(carry6_3,sum6_3,P6_3,sum5_4,carry5_3);
wire [1] carry6_2;
wire [1] sum6_2;
fa1a(carry6_2,sum6_2,P6_2,sum5_3,carry5_2);
wire [1] carry6_1;
wire [1] sum6_1;
fa1a(carry6_1,sum6_1,P6_1,sum5_2,carry5_1);
wire [1] carry6_0;
wire [1] sum6_0;
fa1a(carry6_0,sum6_0,P6_0,sum5_1,P5_0);
wire [1] carry7_6;
wire [1] sum7_6;
fa1a(carry7_6,sum7_6,P7_6,sum6_7,carry6_6);
wire [1] carry7_5;
wire [1] sum7_5;
fa1a(carry7_5,sum7_5,P7_5,sum6_6,carry6_5);
wire [1] carry7_4;
wire [1] sum7_4;
fa1a(carry7_4,sum7_4,P7_4,sum6_5,carry6_4);
wire [1] carry7_3;
wire [1] sum7_3;
fa1a(carry7_3,sum7_3,P7_3,sum6_4,carry6_3);
wire [1] carry7_2;
wire [1] sum7_2;
fa1a(carry7_2,sum7_2,P7_2,sum6_3,carry6_2);
wire [1] carry7_1;
wire [1] sum7_1;
fa1a(carry7_1,sum7_1,P7_1,sum6_2,carry6_1);
wire [1] carry7_0;
wire [1] sum7_0;
fa1a(carry7_0,sum7_0,P7_0,sum6_1,carry6_0);
//0: Generating fa
wire [1] carry8_0;
ha1a(carry8_0,Z[0],carry7_0,sum7_1);
//2: Generating fa
wire [1] carry8_1,sum8_1;
fa1a(carry8_1,Z[1],carry7_1,carry8_0,sum7_2);
//2: Generating fa
wire [1] carry8_2,sum8_2;
fa1a(carry8_2,Z[2],carry7_2,carry8_1,sum7_3);
//2: Generating fa
wire [1] carry8_3,sum8_3;
fa1a(carry8_3,Z[3],carry7_3,carry8_2,sum7_4);
//2: Generating fa
wire [1] carry8_4,sum8_4;
fa1a(carry8_4,Z[4],carry7_4,carry8_3,sum7_5);
//2: Generating fa
wire [1] carry8_5,sum8_5;
fa1a(carry8_5,Z[5],carry7_5,carry8_4,sum7_6);
//1: Generating fa
wire [1] carry8_6,sum8_6;
fa1a(Z[7],Z[6],sum7_7,carry8_5,carry7_6);
endmodule
